From 75adaf2defe86af00c263e2fe2db4219a3644709 Mon Sep 17 00:00:00 2001 From: Thomas Quinot Date: Sat, 30 May 2026 20:23:40 +0200 Subject: [PATCH] Minor reformatting --- _source/_posts/2024-05-01-cosmac.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/_source/_posts/2024-05-01-cosmac.md b/_source/_posts/2024-05-01-cosmac.md index 9be6d47..cac5703 100644 --- a/_source/_posts/2024-05-01-cosmac.md +++ b/_source/_posts/2024-05-01-cosmac.md @@ -68,12 +68,12 @@ System worked on first try except for LOAD mode flip-flop. The 4027 from AliExpress behaves in a weird way, as though J and K were reversed. The expectation is: -* ~DMA-IN is cabled to ~Q (i.e. the active low DMA IN signal is inactive when Q=0 ~Q=1) -* at startup Q=0 ~Q=1 -* upon a raising edge of CLOCK, the flip flop transitions to Q=1 / ~Q=0 / DMA IN is active -* upon a positive signal on RESET, the flip flop transitions to Q=0 / ~Q=1 / DMA IN is inactive +* ~DMA-IN~ is cabled to ~Q~ (i.e. the active low DMA IN signal is inactive when Q=0 ~Q~=1) +* at startup Q=0 ~Q~=1 +* upon a raising edge of CLOCK, the flip flop transitions to Q=1 / ~Q~=0 / DMA IN is active +* upon a positive signal on RESET, the flip flop transitions to Q=0 / ~Q~=1 / DMA IN is inactive According to both the truth table and the circuit design, this is the behaviour that should be observed with J=1 K=0. In practice this is the behaviour observed with J=0 K=1. -If I set J=1 K=0 and set Q=1 by presenting a positive signal on SET, then on a raising edge of CLOCK I see the flip flop going to Q=0 ~Q=1. \ No newline at end of file +If I set J=1 K=0 and set Q=1 by presenting a positive signal on SET, then on a raising edge of CLOCK I see the flip flop going to Q=0 ~Q~=1. \ No newline at end of file